Intel breathless with Nehalem anticipation

[Dashken]

SAN FRANCISCO--This Nehalem plan better work out for Intel, because the chipmaker set very high expectations for the next-generation processor design Tuesday.

Pat Gelsinger, general manager of Intel's Digital Enterprise Group, demonstrated a Nehalem-based system at the Intel Developer Forum here that he said will bring major performance improvements for the company's x86 processor line. The processor family itself is due to arrive in 2008.

The Nehalem demonstration featured a system with two quad-core processors; each processing core can handle two independent instruction sequences called threads, and the demo showed all 16 threads at work on various tasks. The processor was the very first incarnation of Nehalem--the "A0" version--built for the first time three weeks ago, Gelsinger said.

"What you saw today was incredible health," he boasted during a meeting with reporters after the speech. "It really is pretty spectacular, and we're excited by the progress."

Nehalem brings major changes not just to the processor but also to the way in which it communicates with memory and other processors, a technology formerly called CSI, which variously stood for Common System Interconnect or Interface, and now branded as QuickPath Interconnect, or QPI. QuickPath reproduces a technique that rival Advanced Micro Devices used for years to market share against Intel and secure a solid position in all four major server makers' product lines.

The Nehalem processors demonstrated Tuesday each had four cores on a single slice of silicon, the approach AMD uses with its new Barcelona member of the Opteron processor family. In 2009, Intel will sell Nehalem processors with eight cores on a single slice of silicon.

Intel also is expected to sell less expensive Nehalem processors with dual cores per die, a source familiar with the company's plans said.

Gelsinger offered few specifics about the Nehalem performance, but said QuickPath will dramatically help with a major performance bottleneck, the delay in fetching data from memory.

"When we go to Nehalem next year, we will see the memory latency and bandwidth improve dramatically," Gelsinger said. Memory bandwidth will be three times that of today's best systems, he said.

Intel countered AMD in part by including large amounts of cache memory that can keep information readily on hand for processors instead of requiring them to fetch it from main memory. Intel won't drop its cache when it moves to QuickPath, he said, promising glorious results.

"We've made up for (AMD's) better system architecture with superior caching," Gelsinger said. "When we bring those big caches over to Nehalem, wow."

AMD's QuickPath rival, the Direct Connect architecture that debuted in 2003 with the Opteron and Athlon 64 processors, gave the company years of advantage over Intel. But more recent troubles there have shown that Direct Connect on its own wasn't enough to keep Intel at bay. Intel, meanwhile, restored its competitiveness by improving its chips' performance and energy efficiency.

QuickPath involves two main ingredients. One is a built-in component called a memory controller that is separate on today's Intel chips; integrating the memory controller can reduce communication delays in transferring data to and from memory, and AMD has kept its performance edge when it comes to memory-intensive tasks.

The second component is a direct connection among processors, which lets chips share data and lets one processor fetch information stored in memory attached to another processor. With today's technology, such communications take place through a separate processor, the "north bridge" element of the chipset that accompanies central processors.

Both of Intel's major processor lines--the mainstream x86 models such as Pentium and the Itanium models geared for the high-end servers--will use QuickPath.

Sun Microsystems showed an as-yet-unannounced server with four quad-core Intel processors at IDF. John Fowler, Sun's executive vice president of systems, said the 3.5-inch-thick system has all the memory, backup systems and storage as competitors' servers but is half the height.

To fight back against AMD, Intel embarked on a "tick-tock" strategy to improve its chip performance. In odd-numbered years, it moves to a new manufacturing process that permits smaller-scale chip features. In even-numbered years come new chip architectures.

This November, the "tick" will be the arrival of Penryn chips, which reproduce the designs of today's Core processors. The circuit features of Intel's chips today use 65-nanometer features, but Penryn models are built with 45-nanometer features, letting chip sizes be shrunk considerably.

In 2008 will come the "tock": Nehalem's new architecture built using Penryn's 45-nanometer process.

Source: http://www.news.com/8301-10784_3-9780925-7.html

[Adrian Wong]

It's about time for Intel to move away from the FSB and add an on-die memory controller.