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| Hold me back! I can't stop posting!!! Join Date: 16 Dec 2002 Location: Floating Island Of Mandango
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Reputation: 3294 ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() Rep Power: 48 | did a few round of benchie lately. what do you guys think? Why spend more on high-performance RAM? doesn't improve the performance that much. Low latencies have little impact on the Core architecture. very diff from the K8/X2
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| Administrator Join Date: 6 Oct 2002 Location: Maranello
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Reputation: 4649 ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() Rep Power: 82 | This is the exact topic that we have been discussing in the IRC. While theoratically, the memory bandwidth is higher, in real world situation, it hardly makes any difference. For me, getting a DDR2-1000 memory is solely for overclocking purposes when reaching 500MHz with 1:1. Maybe some other benchmarks will show a bigger difference? |
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| Hold me back! I can't stop posting!!! Join Date: 16 Dec 2002 Location: Floating Island Of Mandango
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Reputation: 3294 ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() Rep Power: 48 | Quote:
I cant run more benchies at the moment. am stuck with other stuff.. here is another one. missed it this morning. 1333FSB, 4-4-4-12. 1T for 667 and 800, 2T for 1066. as u can see, increased FSB doesnt improve the performance much as well. mem isnt the bottleneck.
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| Da Boss Join Date: 10 Oct 2002 Location: In front of my ASUS F8V notebook!
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Reputation: 3730 ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() Rep Power: 78 | Hmm.. Were you testing with a 2MB cached C2D or a 4MB cached one? ![]()
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| | #7 (permalink) |
| Hold me back! I can't stop posting!!! Join Date: 16 Dec 2002 Location: Floating Island Of Mandango
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Reputation: 3294 ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() Rep Power: 48 | 4mb. i used C2Q because it's "supposedly" more bandwidth demanding. but then again, higher bandwidth/lower latency do not help much. i supposed desktop app just isn't enough to stress the quad, or the prefetcher and caching system of the Core arch. is doing a damn good job.
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| | #8 (permalink) |
| I'm a regular Join Date: 17 Oct 2006
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Reputation: 234 ![]() ![]() ![]() Rep Power: 6 | generally nowadays, it's not latency's that matter as archetecturally, C2D is not bandwidth hungry. It's more to cache hungry rather more then anything else. That's why we're seeing better gains scaling FSB using loose timings compared to tighter timings but lower FSB's. I think anand and THG did cover this when C2D was launched or something. And anyway, since DDR2 runs at 4 bits per cycle, you actually have greater data transfer I/O's compared to DDR (2 bit), so the losses in timing latency's is negated already |
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