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| | #51 (permalink) |
| News Writer Join Date: 23 Apr 2006
Posts: 1,173
Reputation: 716 ![]() ![]() ![]() ![]() ![]() ![]() ![]() Rep Power: 11 | oh... u missed out Q6600 (2.4Ghz w/ locked multi, TDP 105W): http://www.legitreviews.com/news/2763/ http://www.techspot.com/review/36-in...e2-quad-q6600/ http://www.firingsquad.com/hardware/...q6600_preview/ http://www.hardware.info/productdb/b..._2_Quad_Q6600/ http://www.theinquirer.net/default.aspx?article=36494 |
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| | #52 (permalink) |
| Active Join Date: 3 Mar 2005
Posts: 642
Reputation: 138 ![]() ![]() Rep Power: 5 | Yep that is wrong as the E6320 & E6420 are suppose to have 4MB of L2 cache.
__________________ Guns don't kill people, Chuck Norris kills people! |
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| | #53 (permalink) | |
| h@x! Join Date: 11 Aug 2003 Location: Sarawak, Malaysia.
Posts: 11,293
Reputation: 2024 ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() Rep Power: 37 | Quote:
nvm, going to update it again and correct the mistakes.They ARE exactly the same except the 4MB L2 part
__________________ Max_87 Tech ARP http://www.techarp.com P4 630 Last edited by Max_87 : 12th Feb 2007 at 02:39 AM. | |
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| | #54 (permalink) | |
| h@x! Join Date: 11 Aug 2003 Location: Sarawak, Malaysia.
Posts: 11,293
Reputation: 2024 ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() Rep Power: 37 | Quote:
__________________ Max_87 Tech ARP http://www.techarp.com P4 630 | |
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| | #55 (permalink) |
| Newbie Join Date: 12 Feb 2007
Posts: 1
Reputation: 0 ![]() Rep Power: 0 | You have the 'instruction sets supported' columns, and in them, you list "CISC" and "RISC" as instruction sets. That's like saying you were robbed by a guy wearing 'pastel' or 'bright'. They are descriptions of the instruction set, not instruction sets themselves. (IA32/x86, IA64 (Itanium,) and AMD64/x86-64/x64/EM64T are instruction set names.) Not to mention you're wrong on many of them. All current x86 processors present themselves to the OS as CISC processors. The fact that deep down, they operate more like RISC processors has no actual effect on anything. You might as well also list superscalar and out-of-order execution if you're going to list CISC and RISC. (And everything Pentium Pro and up, including all Pentium II and Celeron processors, are 'RISC at heart'.) Also, only the graphical logo for the Pentium 3 does it look like "Pentium !!!". Everywhere else, it is "Pentium III" (See here for a sample.) And *ALL* Pentium III's, even the Katmai's, include SSE. That is what made it different than the Pentium II. |
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| | #58 (permalink) |
| News Writer Join Date: 23 Apr 2006
Posts: 1,173
Reputation: 716 ![]() ![]() ![]() ![]() ![]() ![]() ![]() Rep Power: 11 | btw, where did u find the news on the Q4/06 release of X6900? i googled n all i find is "preview" & so-call "reviews" while they all use X6800 overclocked not seen a cpu-z screenshot nor photo of the chip ![]() |
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| | #59 (permalink) | |
| h@x! Join Date: 11 Aug 2003 Location: Sarawak, Malaysia.
Posts: 11,293
Reputation: 2024 ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() Rep Power: 37 | Quote:
![]() Anyway, updating the stuffs now
__________________ Max_87 Tech ARP http://www.techarp.com P4 630 | |
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