There is virtually no optimization penalty for tri-core. The thread scheduling is all done by the OS, not the application itself. As long as the...
Yes you are right. C1 is an automated mechanism. The 'E' behind is just a new feature to enable the clock and voltage throttling before C1 kicks in.
Welcome dude :) Yea, because C1 is sleep state, the whole core is put down into HALT mode. C0 is active, so even the processor runs at lowest...
That is the sole purpose of P-state (Performance State). It manages the processor to give the best performance per watt. A simple question for...
If you are really interested to know how EIST work, I can start from the basic. First of all, EIST is controlled by writing some value to...
Yes I am absolutely sure about EIST. 1. EIST (a.k.a. P-state) requires OS support, I mentioned in the guide. 2. C1E uses EIST circuit to lower...
nice piece of info :thumb:
Got desktop and mobile version la, the codename still the same, but marketing name maybe very different :p
There will be another type of Celeron 4xx with 1MB L2, probably Intel will name it Core 2 Solo =P Engineering Sample will be out pretty soon,...
Yea, Sempron is really cheap, but the performance isn't good. From Tomshardware CPU Power chart, Sempron is godlike in terms of power consumption....
It is actually around 25 - 30W when full load and averaging about 15-20W :thumb: I am still waiting for my single core to arrive. Time unknown yet :p
Thanks dude. Alrite, here is your answer EIST - manages processor P-state in the C0 state only. C1E - manages processor P-state in C1 state,...
This is not my view, but specification says so. C1 does not mentioned anything about FID/VID, but C1E does mentioned. C1: execute HLT instruction...
Thanks for the feedbacks guys :dance:
You guys can shoot me questions here. I'll answer them whenever I am free. Dashken, is it possible to update my conclusion with this link?...
Separate names with a comma.
