Intel Xeon Integrated Memory Controller (ICM), management policies.

Discussion in 'Processors, Motherboards & Memory' started by portillo, Mar 29, 2013.

  1. portillo

    portillo Newbie


    I'm curios to know more about the DRAM management policies embedded in an Intel or AMD ICM. I already tried to read the technical Intel 5520 chip-set Data-Sheet but is very cryptic (e.g., API C .- Advanced Programmable Interrupt Controller [And that's all the info available])

    From your past experience, is there another way to find more information?

    Do you know if in specific the Row Buffer Management Policy is embedded in the processor chip set?

    I just need someone to point me in the right direction, Thanks!
  2. Adrian Wong

    Adrian Wong Da Boss Staff Member

    Hi portillo,

    The usual row buffer management policy used in desktop chipsets is open-page. Server chipsets, on the other hand, use the closed-page policy because it favours random accesses to different memory rows.

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