PCI Master Bus Timeout

Discussion in 'BIOS Optimization Guide (BOG)' started by invid1729, Sep 30, 2005.

  1. invid1729

    invid1729 Newbie

    Chipset: VIA KT133A
    Bios Setting: PCI Master Bus Timeout
    Options: 0, 1, 2, ..., 15

    I don't think i entirely understand everything here: so after the pci master timeout, if i have PCI Delayed Transaction enabled, then either the target or master is put into this delayed transaction mode (which is supposed to prevent the bus from idling, right?) instead of requiring the bus to be rearbitrated, is that correct?

    well, my options for PCI Master Bus TImeout are 0 - 15 (I'm assuming this is clock cycles)--I don't understand this timeout thing well enough to know whether having a longer timeout (e.g. 15 cycles) or shorter timeout is more beneficial. could anyone clear this up for me?

  2. Adrian Wong

    Adrian Wong Da Boss Staff Member

    Actually, PCI Delayed Transaction does not prevent bus idling.

    It merely allows the device which has not completed its transaction (within the maximum target latency) to continue the transaction while the bus access is granted to another device.

    PCI Master Bus Timeout is a totally different feature altogether. In fact, it's actually misnamed - the correct term is PCI Bus Master Timeout. :mrgreen:

    In any case, I've put it down for inclusion in a BOG update soon.

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